Display device and manufacturing method thereof

ABSTRACT

A display device according to an exemplary embodiment includes: a substrate including a display area and a peripheral area; a thin film transistor positioned in the display area of the substrate; a first electrode connected to the thin film transistor; a roof layer positioned on the first electrode and spaced apart from the first electrode by a microcavity that is interposed between the roof layer and the first electrode; a liquid crystal layer positioned inside the microcavity; an encapsulation layer positioned on the roof layer; a pad portion positioned in the peripheral area of the substrate; and a pillar positioned in the peripheral area of the substrate.

RELATED APPLICATIONS

This application claims priority to and the benefit of Korean PatentApplication No. 10-2016-0001934 filed in the Korean IntellectualProperty Office on Jan. 7, 2016, the disclosure of which is incorporatedby reference in its entirety.

BACKGROUND

1. Field

The present disclosure relates generally to a display device and amanufacturing method thereof.

2. Description of the Related Art

As one of the most widely used flat panel displays, a liquid crystaldisplay (LCD) includes two sheets of display panels formed withfield-generating electrodes and a liquid crystal layer interposedtherebetween. The LCD displays an image by generating an electric fieldin a liquid crystal layer by applying a voltage to the field-generatingelectrodes, determining alignment directions of liquid crystal moleculesof the liquid crystal layer by the generated electric field, andcontrolling polarization of incident light.

The two sheets of display panels included in the LCD may be a thin filmtransistor array panel and an opposed display panel. In the thin filmtransistor array panel, a gate line for transmitting a gate signal and adata line for transmitting a data signal are formed to cross each other.In addition, a thin film transistor connected to the gate and data linesand a pixel electrode connected to the thin film transistor may beformed in the thin film transistor array. A light blocking member, acolor filter, a common electrode, and the like may be formed in theopposed display panel or in the thin film transistor array panel.

In conventional LCDs, since two sheets of substrates are required andcomponents are respectively formed on the two sheets of substrates, thedisplay device not only becomes heavy, thick, and costly, but alsorequires a longer processing time.

The above information disclosed in this Background section is only toenhance the understanding of the background information of the describedtechnology and therefore it may contain information that does not form aprior art that is already known to a person of ordinary skill in theart.

SUMMARY

The present disclosure provides a display device and a manufacturingmethod thereof that are capable of reducing a thickness, a width, acost, and a processing time by manufacturing the display device usingone substrate.

As such, when the display device is manufactured using one substrate, anencapsulation layer for encapsulating a liquid crystal layer may beformed. In order for a pad portion to be connected to an outsideterminal, the pad portion should be formed such that it is not coveredby the encapsulation layer.

When the encapsulation layer is partially coated only in the displayarea, there may be a large area of the encapsulation layer with a slopeat starting and ending points of the coating, and such an area cannot beused as the display area, thereby increasing a bezel area.

In addition, when the encapsulation layer is formed across the entiredisplay area and is then patterned to open the pad portion, there is aproblem in that the liquid crystal layer positioned inside the displayarea may be contaminated during a photolithography process.

The present disclosure provides a display device and a manufacturingmethod thereof that are capable of opening a pad portion withoutcontaminating a liquid crystal layer.

An exemplary embodiment provides a display device, including: asubstrate including a display area and a peripheral area; a thin filmtransistor positioned in the display area of the substrate; a firstelectrode connected to the thin film transistor; a roof layer positionedon the first electrode and spaced apart from the first electrode by amicrocavity that is interposed between the roof layer and the firstelectrode; a liquid crystal layer positioned inside the microcavity; anencapsulation layer positioned on the roof layer; a pad portionpositioned in the peripheral area of the substrate; and a pillarpositioned in the peripheral area of the substrate.

The pillar may include a first layer that is made of the same materialas the roof layer.

The display device may further include an insulating layer positionedunder the roof layer, wherein the pillar may further include a secondlayer that is made of the same material as the insulating layer.

The display device may further include a second electrode positionedbetween the roof layer and the liquid crystal layer, wherein the pillarmay further include a third layer that is made of the same material asthe second electrode.

The pillar may be formed by laminating the third layer, the secondlayer, and the first layer.

The display device may further include a second electrode and aninterlayer insulating layer interposed between the first electrode andthe second electrode, wherein the liquid crystal layer may be positionedon the second electrode.

The display device may further include an insulating layer positionedunder the roof layer, wherein the pillar may include a first layer thatis made of the same material as the roof layer, and a second layer thatis positioned under the first layer and is made of the same material asthe insulating layer.

The display device may further include a gate line and a data lineconnected to the thin film transistor, a gate pad positioned in theperipheral area of the substrate and connected to the gate line, a gatecontact assistant positioned on the gate pad, a data pad positioned inthe peripheral area of the substrate and connected to the data line, anda data contact assistant positioned on the data pad.

A side surface of the encapsulation layer may include a heat-deformableportion.

A manufacturing method of a display device according to an exemplaryembodiment may include: forming a thin film transistor on a display areaof a substrate including a display area, a peripheral area, and an extraarea; forming a first electrode to be connected to the thin filmtransistor; forming a sacrificial layer on the first electrode; forminga roof layer on the sacrificial layer; forming a microcavity between thefirst electrode and the roof layer by removing the sacrificial layer,forming an encapsulation layer on the roof layer; cutting theencapsulation layer positioned on a boundary between the display areaand peripheral area of the substrate; cutting a boundary between theperipheral area and extra area of the substrate; and removing theencapsulation layer positioned in the peripheral area and extra area ofthe substrate, and the extra area of the substrate.

The manufacturing method may further include forming a gate line on thesubstrate, and forming a data line on the substrate, wherein the gateline and the data line may be connected to the thin film transistor.

The manufacturing method may further include forming, in the peripheralarea of the substrate, a gate pad portion connected to the gate line,and forming, in the peripheral area of the substrate, a data pad portionconnected to the data line.

The manufacturing method may further include forming the sacrificiallayer on the gate pad portion and the data pad portion, and forming adummy microcavity.

The manufacturing method may further include removing the dummymicrocavity, and forming a pillar in the peripheral area of thesubstrate.

The pillar may include a first layer that is made of the same materialas the roof layer.

The manufacturing method may further include forming a second electrodeon the sacrificial layer; and forming an insulating layer on the secondelectrode, wherein the pillar further includes a second layer that ispositioned under the first layer and is made of the same material as theinsulating layer, and a third layer that is positioned under the secondlayer and is made of the same material as the second electrode.

The manufacturing method may further include forming a second electrode;and forming an interlayer insulating layer interposed between the firstelectrode and the second electrode; and forming an insulating layer onthe sacrificial layer, wherein the pillar further may include a secondlayer that is positioned under the first layer and is made of the samematerial as the insulating layer.

The forming of the gate pad portion may include forming a gate padextended from an end portion of the gate line, and forming a gatecontact assistant on the gate pad.

The gate pad is made of the same material as the gate line, and the gatecontact assistant may be made of the same material as the firstelectrode.

The forming of the data pad portion may include forming a data padextended from an end portion of the data line, and forming a datacontact assistant on the data pad.

The data pad may be made of the same material as the data line, and thedata contact assistant may be made of the same material as the firstelectrode.

The manufacturing method may further include irradiating a laser to theencapsulation layer positioned on a boundary between the display areaand peripheral area of the substrate to cut the encapsulation layer.

A region to which a laser is irradiated may not overlap the gate padportion or the data pad portion.

A side surface of the encapsulation layer may include a heat-deformableportion.

The display device and the manufacturing method thereof according to thecurrent exemplary embodiment as described above have the followingeffects.

According to the current exemplary embodiment, since the display deviceis manufactured using one substrate, the weight, thickness, cost, andprocessing time thereof can be reduced.

In addition, after forming the dummy microcavity in the peripheral area,the encapsulation layer and the substrate can be removed using a lasercutting process to open the pad portion, thereby preventingcontamination of the liquid crystal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of a display device, according to an exemplaryembodiment.

FIG. 2 is a partial top plan view of a display device, according to anexemplary embodiment.

FIG. 3 is a cross-sectional view of a display device taken along theline III-III of FIG. 2.

FIG. 4 is a cross-sectional view of a display device taken along theline IV-IV of FIG. 2.

FIGS. 5 to 18 are process cross-sectional views of a manufacturingmethod of a display device, according to an exemplary embodiment.

FIG. 19 is a partial top plan view of a display device, according to anexemplary embodiment.

FIG. 20 is a cross-sectional view of the display device taken along theline XX-XX of FIG. 19.

FIG. 21 is a cross-sectional view of the display device taken along theline XXI-XXI of FIG. 19.

DETAILED DESCRIPTION

The present disclosure will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the present disclosure are shown. As those skilled in the art wouldrealize, the described embodiments may be modified in various differentways, without departing from the spirit or scope of the presentdisclosure.

In the drawings, the thickness of layers, films, panels, regions, etc.may be exaggerated for clarity. Like reference numerals designate likeelements throughout the specification. It will be understood that whenan element such as a layer, film, region, or substrate is referred to asbeing “on” another element, it can be directly on the other element orone or more intervening elements may also be present. In contrast, whenan element is referred to as being “directly on” another element, theremay be no intervening elements present.

Referring first to FIG. 1, a display device according to an exemplaryembodiment will be described as follows.

FIG. 1 is a top plan view of a display device, according to an exemplaryembodiment. The display device includes a substrate 110 that is made ofa material such as glass or plastic.

The substrate 110 is divided into a display area DA and a peripheralarea PA. The display area DA is positioned in a center part of thesubstrate 110, and the peripheral area PA surrounds an edge of thedisplay area DA. The display area DA is an area on which an image isdisplayed, and drivers for transmitting driving signals are positionedin the peripheral area PA to allow the image to be displayed in thedisplay area DA.

In the display area DA, a plurality of gate lines G1 to Gn are formed tobe parallel to each other, and a plurality of data lines D1 to Dm areformed to be parallel to each other. The plurality of gate lines G1 toGn and the plurality of data lines D1 to Dm are insulated from eachother, and cross each other to define a plurality of pixels.

In each pixel, a thin film transistor Q an LC capacitor Clc, and astorage capacitor Cst are formed. A control terminal of the thin filmtransistor Q is connected to any one of the plurality of gate lines G1to Gn, an input terminal thereof is connected to any one of theplurality of data lines D1 to Dm, and an output terminal thereof isconnected to one terminal of the LC capacitor Clc and one terminal ofthe storage capacitor Cst. A common voltage may be applied to the otherterminal of the LC capacitor Clc, and a reference voltage may be appliedto the other terminal of the storage capacitor Cst.

The gate lines G1 to Gn and the data lines D1 to Dm are extended to theperipheral area PA. In the peripheral area PA, gate pad portions GPconnected to the gate lines G1 to Gn are positioned, and data padportions DP connected to the data lines D1 to Dm are positioned. Thegate pad portions GP may be connected to an outside terminal, andreceive a gate signal from a gate driver to transmit the gate signal tothe gate lines G1 to Gn. The data pad portions DP may be connected to anoutside terminal, and receive a data signal from a data driver totransmit the data signal to the data lines D1 to Dm.

In FIG. 1, the gate pad portions GP are illustrated to be positioned ata left edge of the display area DA, but the present disclosure is notlimited thereto, and the position of the gate pad portions GP may bevariously changed. Alternatively, the gate pad portions GP may bepositioned at opposite lateral edges of the display area DA.

In FIG. 1, the data pad portions DP are illustrated to be positioned atan upper edge of the display area DA, but the present disclosure is notlimited thereto, and the position of the data pad portions DP may bevariously changed. Alternatively, the data pad portion DP may bepositioned at both lateral edges of the display area DA.

Structures of one pixel and pad portions of a display device accordingto an exemplary embodiment will now be described with reference to FIGS.2 to 4.

FIG. 2 is a partial top plan view of a display device according to anexemplary embodiment. FIG. 3 is a cross-sectional view of the displaydevice taken along the line III-III of FIG. 2. FIG. 4 is across-sectional view of the display device taken along the line IV-IV ofFIG. 2.

Referring to FIGS. 2 to 4, a gate line 121, a gate electrode 124protruding from the gate line 121, and a gate pad 125 connected to thegate line 121 are positioned on a substrate 110. The gate line 121extends in a first direction and transmits a gate signal. For example,the gate line 121 may extend in a substantially horizontal direction. Inthe top plan view, the gate electrode 124 protrudes upward of the gateline 121. However, the present disclosure is not limited thereto, and aprotruding shape and direction of the gate electrode 124 may bevariously modified. Alternatively, the gate electrode 124 may notprotrude from the gate line 121, and may be disposed on the gate line121. The gate line 121 and the gate electrode 124 are positioned in thedisplay area DA, and the gate line 121 is extended to the peripheralarea PA.

The gate pad 125 is extended from an end portion of the gate line 121.The end portion of the gate line 121 is positioned in the peripheralarea PA, and the gate pad 125 is positioned in the peripheral area PA.The gate pad 125 may have a wider width than the gate line 121. The gatepad 125 may be made of the same material as the gate line 121 and thegate electrode 124, and may be disposed on the same layer.

A reference voltage line 131 and storage electrodes 135 a and 135 bprotruding from the reference voltage line 131 may be further formed onthe substrate 110. The reference voltage line 131 extends in a directionparallel to the gate line 121, and is spaced apart from the gate line121. A constant voltage may be applied to the reference voltage line131. The storage electrodes 135 a and 135 b include a pair of firststorage electrodes 135 a extending substantially perpendicular to thereference voltage line 131, and a second storage electrode 135 bextending substantially parallel to the reference voltage line 131 andconnecting a pair of first storage electrodes 135 a. The referencevoltage line 131 and the storage electrodes 135 a and 135 b may surrounda pixel electrode 191.

A gate insulating layer 140 is formed on the gate line 121, the gateelectrode 124, the gate pad 125, the reference voltage line 131, and thestorage electrodes 135 a and 135 b. The gate insulating layer 140 may bemade of an inorganic insulating material such as a silicon nitride(SiNx) and a silicon oxide (SiOx). In addition, the gate insulatinglayer 140 may include a single layer or multiple layers.

A semiconductor 154 is formed on the gate insulating layer 140. Thesemiconductor 154 may be disposed on the gate electrode 124. Thesemiconductor 154 may be made of amorphous silicon, polycrystallinesilicon, or a metal oxide.

An ohmic contact member (not shown) may be disposed on the semiconductor154. The ohmic contact member may be made of a silicide or a materialsuch as n+hydrogenated amorphous silicon in which an n-type impurity isdoped at a high concentration.

A data line 171, a source electrode 173, a drain electrode 175, and adata pad 177 are formed on the semiconductor 154 and the gate insulatinglayer 140. The data line 171 transmits a data signal and extends in asecond direction to cross the gate line 121 and the reference voltageline 131. For example, the data line 171 may extend in a substantiallyvertical direction. The source electrode 173 protrudes above the gateelectrode 124 from the data line 171, and may be bent in a U-shape. Thedrain electrode 175 includes a wide end portion and a rod-shaped endportion. The wide end portion of the drain electrode 175 overlaps thepixel electrode 191. The rod-shaped end portion of the drain electrode175 is partially surrounded by the source electrode 173. However, thepresent disclosure is not limited thereto, and shapes of the sourceelectrode 173 and the drain electrode 175 may be variously modified. Thedata line 171, the source electrode 173, and the drain electrode 175 arepositioned in the display area DA, and the data line 171 is extended tothe peripheral area PA.

The data pad 177 is connected to the data line 171. The data pad 177 isextended from an end portion of the data line 171. The end portion ofthe data line 171 is positioned in the peripheral area PA, and the datapad 177 is positioned in the peripheral area PA. The data pad 177 mayhave a wider width than the data line 171. The data pad 177 may be madeof the same material as and disposed on the same layer as the data line171, the source electrode 173, and the drain electrode 175.

The gate electrode 124, the source electrode 173, and the drainelectrode 175 form one thin film transistor (TFT) Q along with thesemiconductor 154. In this case, a channel of the thin film transistor Qis formed in the semiconductor 154 between the source electrode 173 andthe drain electrode 175.

A passivation layer 180 is formed on the data line 171, the sourceelectrode 173, the drain electrode 175, the semiconductor 154 exposedbetween the source electrode 173 and the drain electrode 175, and thedata pad 177. The passivation layer 180 may be made of an organicinsulating material or an inorganic insulating material, and may includea single layer or multiple layers.

On the passivation layer 180, color filters 230 are formed inside eachpixel. Each color filter 230 may display one of three primary colorssuch as red, green, and blue. The color filter 230 may not be limited todisplaying the three primary colors such as red, green, and blue, butmay display cyan, magenta, yellow, and white-based colors.

A light blocking member 220 is formed between adjacent color filters230. The light blocking member 220 may be positioned at an edge of thepixel, and may overlap the gate line 121, the data line 171, and thethin film transistor Q to prevent light leakage. However, the presentdisclosure is not limited thereto, and the light blocking member 220 mayoverlap the gate line 121 and the thin film transistor Q, but not thedata line 171. In this case, in order to prevent light leakage, theadjacent color filters 230 may overlap each other in a portion where thelight blocking member 220 overlaps the data line 171. The color filter230 and the light blocking member 220 may overlap each other in someregions.

A first insulating layer 240 may be formed on the color filter 230 andthe light blocking member 220. The first insulating layer 240 may bemade of an organic insulating material, and may serve to planarize topsurfaces of the color filter 230 and the light blocking member 220. Thefirst insulating layer 240 may be a dual layer that includes a layermade of an organic insulating material and a layer made of an inorganicinsulating material. Alternatively, the first insulating layer 240 maybe omitted in some embodiments.

A first contact hole 181 exposing at least a portion of the drainelectrode 175 is formed in the first insulating layer 240, the lightblocking member 220, and the passivation layer 180. The first contacthole 181 may expose the wide end portion of the drain electrode 175. Inaddition, a second contact hole 185 exposing at least a portion of thegate pad 125 is formed in the passivation layer 180 and the gateinsulating layer 140, and a third contact hole 187 exposing at least aportion of the data pad 177 is formed in the passivation layer 180.

The pixel electrode 191 is formed on the first insulating layer 240. Thepixel electrode 191 may be made of a transparent metal oxide such as anindium tin oxide (ITO) or an indium zinc oxide (IZO). The pixelelectrode 191 is connected to the drain electrode 175 through the firstcontact hole 181. When the thin film transistor Q is turned on, a datavoltage is applied to the drain electrode 175 through the pixelelectrode 191.

The pixel electrode 191 includes a horizontal stem portion 193, avertical stem portion 192, and a minute branch portion 194 extendingfrom the vertical and horizontal stem portions 193 and 192. The pixelelectrode 191 is divided into four subregions by the horizontal stemportion 193 and the vertical stem portion 192. The minute branch portion194 obliquely extends from the horizontal stem portion 193 and thevertical stem portion 192, and may form an angle of about 45° or about135° with an extending direction of the gate line 121 or the horizontalstem portion 193. In addition, extending directions of the minute branchportions 194 of the two adjacent subregions may be perpendicular to eachother. In the current exemplary embodiment, the pixel electrode 191 mayfurther include an outer stem portion that surrounds an outer edge ofthe pixel.

In addition, a gate contact assistant 195 and a data contact assistant197 are positioned in the peripheral area PA of the substrate 110. Thegate contact assistant 195 and the data contact assistant 197 may bedisposed on the passivation layer 180. The gate contact assistant 195 isconnected to the gate pad 125 through the second contact hole 185. Thegate contact assistant 195 may be made of the same material as anddisposed on the same layer as the pixel electrode 191. The gate pad 125and the gate contact assistant 195 are laminated to form a gate padportion GP. The data contact assistant 197 is connected to the data pad177 through the third contact hole 187. The data contact assistant 197may be made of the same material as and disposed on the same layer asthe pixel electrode 191. The data pad 177 and the data contact assistant197 are laminated to form a data pad portion DP. The pixel electrode 191may be positioned in the display area DA, and the gate contact assistant195 and the data contact assistant 197 may be positioned in theperipheral area PA.

The layout of the pixel, the structure of the thin film transistor, andthe shape of the pixel electrode described above are merely examples,and the present disclosure is not limited thereto and may be variouslymodified. For example, one pixel may include a plurality of subpixels towhich different voltages are respectively applied. For this purpose, aplurality of thin film transistors may be formed in one pixel.

A common electrode 270 is formed on the pixel electrode 191 to be spacedapart from the pixel electrode 191 by a predetermined distance. Amicrocavity 305 is formed between the pixel electrode 191 and the commonelectrode 270. That is, the microcavity 305 is surrounded by the pixelelectrode 191 and the common electrode 270. The common electrode 270 maybe extended in a row direction. The common electrode 270 covers a topsurface and a portion of a side surface of the microcavity 305. A sizeof the microcavity 305 may be variously modified depending on a size andresolution of the display device.

It is illustrated that a plurality of microcavities 305 are positionedon the substrate 110 and one microcavity 305 corresponds to one pixel.However, the present disclosure is not limited thereto, so themicrocavity 305 may correspond to a plurality of pixels, or themicrocavity 305 may correspond to the pixel. When one pixel includes twosubpixels, the microcavity 305 may correspond to one subpixel.Alternatively, the microcavity 305 may correspond to two subpixels thatneighbor each other.

The common electrode 270 may be made of a transparent metal oxide suchas an indium tin oxide (ITO) or an indium zinc oxide (IZO). A constantvoltage may be applied to the common electrode 270, and an electricfield may be generated between the pixel electrode 191 and the commonelectrode 270.

Alignment layers 11 and 21 are formed on the pixel electrode 191 andunder the common electrode 270. The alignment layers 11 and 21 include afirst alignment layer 11 and a second alignment layer 21. The firstalignment layer 11 and the second alignment layer 21 may be verticalalignment layers, and may be made of an aligning material such aspolyamic acid, polysiloxane, or polyimide. The first and secondalignment layers 11 and 21 may be connected at a side wall of an edge ofthe microcavity 305.

The first alignment layer 11 is formed on the pixel electrode 191. Thefirst alignment layer 11 may also be formed directly on the firstinsulating layer 240 that is not covered by the pixel electrode 191. Thesecond alignment layer 21 is formed under the common electrode 270 toface the first alignment layer 11.

A liquid crystal layer including liquid crystal (LC) molecules 310 isformed inside the microcavity 305 that is positioned between the pixelelectrode 191 and the common electrode 270. The LC molecules 310 mayhave negative dielectric anisotropy, and may be disposed perpendicularto the substrate 110 when no electric field is present.

That is, vertical alignment may be achieved.

The pixel electrode 191 to which the data voltage is applied generatesan electric field along with the common electrode 270, therebydetermining alignment directions of the LC molecules 310 positionedinside the microcavity 305 between the pixel electrode 191 and thecommon electrode 270. As such, luminance of light transmitted throughthe liquid crystal layer varies depending on the determined alignmentdirections of the LC molecules 310.

A second insulating layer 350 may be formed on the common electrode 270.The second insulating layer 350 may be made of an inorganic insulatingmaterial such as a silicon nitride (SiNx) or a silicon oxide (SiOx), andmay be omitted in some embodiments.

A roof layer 360 is formed on the second insulating layer 350. The rooflayer 360 may be made of an organic material or an inorganic material.In addition, the roof layer 360 may include a single layer or multiplelayers. The roof layer 360 may be extended in a row direction. The rooflayer 360 covers a top surface of the microcavity 305 and a portion of aside surface of the microcavity 305. The roof layer 360 may be hardenedby a curing process to maintain a shape of the microcavity 305. The rooflayer 360 is formed to be spaced apart from the pixel electrode 191, andthe microcavity 305 is interposed between the pixel electrode 191 andthe roof layer 360.

In the drawings, the color filter 230 is illustrated to be positionedunder the microcavity 305, but the present disclosure is not limitedthereto. The position of the color filter 230 may be changed. Forexample, the roof layer 360 may be made of a color filter material, andin this case, the color filter 230 may be positioned on the microcavity305.

A pillar 500 is positioned in the peripheral area PA of the substrate110. The pillar 500 may be disposed on the passivation layer 180. Thepillar 500 may include a single layer or multiple layers. For example,the pillar 500 may include a first layer 510, a second layer 520positioned under the first layer 510, and a third layer 530 positionedunder the second layer 520. The first layer 510 may be made of the samematerial as and disposed on the same layer as the roof layer 360. Thefirst layer 510 may be thinner than the roof layer 360. The second layer520 may be made of the same material as and disposed on the same layeras the second insulating layer 350. The third layer 530 may be made ofthe same material as and disposed on the same layer as the commonelectrode 270. In some embodiments, the pillar 500 may include only thethird layer 530, or may include only the third layer 530 and the secondlayer 520.

It is illustrated that the pillar 500 does not overlap the gate padportion GP and the data pad portion DP. However, the present disclosureis not limited thereto, and the pillar 500 may overlap a portion of thegate pad portion GP and the data pad portion DP.

The common electrode 270 and the roof layer 360 do not cover the sidesurface of the edge of the microcavity 305, and portions of themicrocavity 305 that are not covered by the common electrode 270 and theroof layer 360 are referred to as injection openings 307 a and 307 b.The injection openings 307 a and 307 b include a first injection opening307 a that exposes a side surface of a first edge of the microcavity305, and a second injection opening 307 b that exposes a side surface ofa second edge of the microcavity 305. The first edge and the second edgeface each other. For example, in the top plan view, the first edge maybe an upper edge of the microcavity 305, and the second edge may be alower edge of the microcavity 305. In a manufacturing process of thedisplay device, since the microcavity 305 is exposed by the injectionopenings 307 a and 307 b, an aligning agent or an LC material may beinjected into the microcavity 305 via the injection openings 307 a and307 b.

A third insulating layer 370 may be formed on the roof layer 360. Thethird insulating layer 370 may be made of an inorganic insulatingmaterial such as a silicon nitride (SiNx) or a silicon oxide (SiOx). Thethird insulating layer 370 may be formed to cover a top surface and/or aside surface of the roof layer 360. The third insulating layer 370 mayserve to protect the roof layer 360 that is made of an organic material,and may be omitted in some embodiments.

The third insulating layer 370 may have substantially the same planarshape as the roof layer 360. The roof layer 360 may include multiplelayers, and in this case, the third insulating layer 370 may correspondto one of multiple layers that constitute the roof layer 360.

An encapsulation layer 390 is formed on the third insulating layer 370.The encapsulation layer 390 is formed to cover the injection openings307 a and 307 b that expose a portion of the microcavity 305. That is,the encapsulation layer 390 may encapsulate the microcavity 305 suchthat the LC molecules 310 positioned inside the microcavity 305 do notleak to the outside. The encapsulation layer 390 may be made of amaterial that does not react with the LC molecules 310 since it contactsthe LC molecules 310. For example, the encapsulation layer 390 may bemade of perylene or the like.

The encapsulation layer 390 is positioned in the display area DA, and isnot positioned in the peripheral area PA. After the encapsulation layer390 is formed in both the display area DA and the peripheral area PA,the encapsulation layer 390 positioned in the peripheral area PA may beremoved, for example, using a laser. The laser may be irradiated to aboundary between the display area DA and the peripheral area PA. As aresult, a side surface of the encapsulation layer 390 may include aheat-deformable portion.

The encapsulation layer 390 may be a multilayer such as a dual layer, atriple layer, or the like. The dual layer includes two layers that aremade of different materials. The triple layer includes three layers, inwhich adjacent layers are respectively made of different materials. Forexample, the encapsulation layer 390 may include a layer that is made ofan organic insulating material and a layer that is made of an inorganicinsulating material.

The encapsulation layer 390 is positioned in the display area DA, and isnot positioned in the peripheral area PA. Accordingly, the gate padportion GP and the data pad portion DP may not be covered by theencapsulation layer 390, but may be exposed.

Although not illustrated, a polarizing plate may be further formed attop and bottom surfaces of the display device. The polarizing plate mayinclude a first polarizing plate and a second polarizing plate. Thefirst polarizing plate may be attached to a bottom surface of thesubstrate 110, and the second polarizing plate may be attached onto theencapsulation layer 390.

Next, with reference to FIG. 5 to FIG. 18, a manufacturing method of adisplay device will be described as follows. In addition, thedescription will be made with reference to FIGS. 1 to 4. FIGS. 5 to 18are process cross-sectional views of a manufacturing method of a displaydevice, according to an exemplary embodiment.

As shown in FIGS. 5 and 6, a gate line 121 extending in a firstdirection and a gate electrode 124 protruding from the gate line 121 areformed on a substrate 110 that is made of glass or plastic. For example,the gate line 121 may substantially extend in a horizontal direction.

In one embodiment, a gate pad 125 connected to the gate line 121 isformed together with the gate line 121 and gate electrode 124. The gateline 121 is extended from a display area DA to a peripheral area PA. Thesubstrate 100 further includes an extra area EA on an outer edge of theperipheral area PA. The gate pad 125 is extended from an end portion ofthe gate line 121 and is positioned in the peripheral area PA. The gatepad 125 may be made of the same material as the gate line 121 and thegate electrode 124, and may be disposed on the same layer.

In addition, a reference voltage line 131 and storage electrodes 135 aand 135 b protruding from the reference voltage line 131 may be formedtogether to be separated from the gate line 121. The reference voltageline 131 extends in a direction parallel to the gate line 121. Thestorage electrodes 135 a and 135 b include a pair of first storageelectrodes 135 a extending substantially perpendicular to the referencevoltage line 131, and a second storage electrode 135 b connecting thepair of first storage electrodes 135 a. The reference voltage line 131and the storage electrodes 135 a and 135 b may surround a pixelelectrode 191.

Next, using an inorganic insulating material such as a silicon nitride(SiNx) or a silicon oxide (SiOx), a gate insulating layer 140 is formedon the gate line 121, the gate electrode 124, the gate pad 125, thereference voltage line 131, and the storage electrodes 135 a and 135 b.The gate insulating layer 140 may include a single layer or multiplelayers.

As shown in FIGS. 7 and 8, a semiconductor material such as amorphoussilicon, polycrystalline silicon, or a metal oxide is deposited on thegate insulating layer 140. Next, a metal material is deposited. Themetal material and the semiconductor material are patterned to form asemiconductor 154, a data line 171, a source electrode 173, a drainelectrode 175, and a data pad 177. The data line 171, the sourceelectrode 173, the drain electrode 175, and the data pad 177 may includea single layer or multiple layers.

The semiconductor 154 is positioned on the gate electrode 124 and underthe data line 171. In the above description, the method in which thesemiconductor material and the metal material are sequentially depositedand are then simultaneously patterned is described, but the presentdisclosure is not limited thereto. After the semiconductor material isdeposited and then patterned such that the semiconductor 154 is formedfirst, the metal material may be deposited and then patterned to formthe data line 171. In this case, the semiconductor 154 may not bepositioned under the data line 171.

The data line 171 extends in a second direction to cross the gate line121 and the reference voltage line 131. For example, the data line 171may be extended in a substantially vertical direction. The sourceelectrode 173 protrudes above the gate electrode 124 from the data line171, and a part of the drain electrode 175 is surrounded by the sourceelectrode 173. The data line 171, the source electrode 173, and thedrain electrode 175 are positioned in the display area DA, and the dataline 171 is extended to the peripheral area PA.

The data pad 177 is connected to the data line 171. The data pad 177 isextended from an end portion of the data line 171. The end portion ofthe data line 171 is positioned in the peripheral area PA, and the datapad 177 is positioned in the peripheral area PA. The data pad 177 may bemade of the same material as and disposed on the same layer as the dataline 171, the source electrode 173, and the drain electrode 175.

The gate electrode 124, the source electrode 173, and the drainelectrode 175 form one thin film transistor (TFT) Q along with thesemiconductor 154. The thin film transistor Q may function as aswitching element that transmits a data voltage of the data line 171. Inthis case, a channel of the switching element is formed in thesemiconductor 154 between the source electrode 173 and the drainelectrode 175.

Next, a passivation layer 180 is formed on the data line 171, the sourceelectrode 173, the drain electrode 175, and an exposed portion of thesemiconductor 154. The passivation layer 180 may be made of an organicinsulating material or an inorganic insulating material, and may includea single layer or multiple layers.

As shown in FIGS. 9 and 10, a color filter 230 is formed on thepassivation layer 180. The color filter 230 may be formed inside eachpixel, and may not be formed at an edge of the pixel. A plurality ofcolor filters 230 allowing different wavelengths to be transmittedtherethrough may be formed. In one embodiment, color filters 230 of thesame color may be formed along a column direction. When forming colorfilters 230 of three colors, a color filter 230 of a first color may beformed first, a mask may be shifted to form a color filter 230 of asecond color, and the mask may be further shifted to form a color filterof a third color.

Subsequently, a light blocking material is used to form a light blockingmember 220 on the passivation layer 180. The light blocking member 220may be positioned at the edge of the pixel, and may overlap the gateline 121, the data line 171, and the thin film transistor Q to preventlight leakage. However, the present disclosure is not limited thereto,and the light blocking member 220 may overlap the gate line 121 and thethin film transistor Q, but not the data line 171.

Next, a first insulating layer 240 is formed on the color filter 230 andthe light blocking member 220. The first insulating layer 240 may beformed of an organic insulating material, and may serve to planarize topsurfaces of the color filter 230 and the light blocking member 220. Thefirst insulating layer 240 may be formed as a dual layer by sequentiallydepositing a layer made of an organic insulating material and a layermade of an inorganic insulating material.

Next, the first insulating layer 240, the light blocking member 220, andthe passivation layer 180 are patterned to form a first contact hole 181that exposes at least a portion of the drain electrode 175. In theforming of the first contact hole 181, a second contact hole 185exposing at least a portion of the gate pad 125 and a third contact hole187 exposing at least a portion of the data pad 177 may be formedtogether therewith.

Next, a transparent metal material such as an indium tin oxide (ITO) oran indium zinc oxide (IZO) is deposited on the first insulating layer240 and then patterned to form the pixel electrode 191. The pixelelectrode 191 is connected to the drain electrode 175 through the firstcontact hole 181. The pixel electrode 191 that has an overallquadrangular shape includes horizontal and vertical stem portions 193and 192 crossing each other, and a minute branch portion 194 extendingfrom the horizontal and vertical stem portions 193 and 192.

In one embodiment, a gate contact assistant 195 and a data contactassistant 197 are formed together therewith the pixel electrode 191. Thegate contact assistant 195 is connected to the gate pad 125 through thesecond contact hole 185, and the data contact assistant 197 is connectedto the data pad 177 through the third contact hole 187. The gate contactassistant 195 and the data contact assistant 197 may be made of the samematerial as and disposed on the same layer as the pixel electrode 191.

As shown in FIGS. 11 and 12, a sacrificial layer 300 is formed on thepixel electrode 191, the gate contact assistant 195, the data contactassistant 197, and the first insulating layer 240. In the top plan view,the sacrificial layer 300 may be formed to extend in the columndirection. The sacrificial layer 300 may be formed in the display areaDA and the peripheral area PA. In the display area DA, the sacrificiallayer 300 may overlap the pixel electrode 191, but not the data line171. In the peripheral area PA, the sacrificial layer 300 may overlapthe gate contact assistant 195 and the data contact assistant 197.

As shown in FIGS. 13 and 14, a transparent metal material such as anindium tin oxide (ITO) or an indium zinc oxide (IZO) is deposited on thesacrificial layer 300 to form a common electrode 270. A secondinsulating layer 350 may be formed on the common electrode 270 using aninorganic insulating material such as a silicon oxide or a siliconnitride. An organic material is coated on the second insulating layer350 and is patterned to form a roof layer 360. In this case, thepatterning may be performed such that an organic material positioned tooverlap the gate line 121 and the thin film transistor Q is removed.Accordingly, the roof layer 360 may be extended along a row direction.

After the roof layer 360 is patterned, light is irradiated to the rooflayer 360 to perform a curing process. The roof layer 360 is hardenedafter performing the curing process, and the roof layer 360 may maintainits shape even if a space is created under the roof layer 360.

Next, portions of the second insulating layer 350 and the commonelectrode 270 positioned to overlap the gate line 121 and the thin filmtransistor Q are removed by patterning the second insulating layer 350and the common electrode 270 using the roof layer 360 as a mask.

Next, an inorganic insulating material such as a silicon nitride (SiNx)or a silicon oxide (SiOx) may be deposited on the roof layer 360 andpatterned to form a third insulating layer 370. In one embodiment, thepatterning may be performed such that the inorganic insulating materialof the portions overlapping the gate line 121 and the thin filmtransistor Q is removed. The third insulating layer 370 may cover a topsurface of the roof layer 360, and may further cover a side surface ofthe roof layer 360. As the roof layer 360, the second insulating layer350, the common electrode 270, and the third insulating layer 370 arepatterned, a portion of the sacrificial layer 300 is exposed to theoutside.

When a developer or a stripper solution is supplied on the sacrificiallayer 300, or an ashing process is performed, the sacrificial layer 300is completely removed, and a microcavity 305 and a dummy microcavity 305a, as shown in FIGS. 15 and 16, are created at the position where thesacrificial layer 300 was previously positioned. The microcavity 305 ispositioned in the display area DA, while the dummy microcavity 305 a ispositioned in the peripheral area PA.

The pixel electrode 191 and the roof layer 360 are spaced apart fromeach other by the microcavity 305 that is interposed between the pixelelectrode 191 and the roof layer 360. The gate contact assistant 195 andthe roof layer 360 are spaced apart from each other by the microcavity305 that is interposed between the gate contact assistant 195 and theroof layer 360. The data contact assistant 197 and the roof layer 360are spaced apart from each other by the microcavity 305 that isinterposed between the data contact assistant 197 and the roof layer360. The roof layer 360 covers a top surface and a portion of a sidesurface of the microcavity 305, and covers a top surface and a portionof a side surface of the dummy microcavity 305 a.

The microcavity 305 is exposed to the outside through portions where theroof layer 360 and the common electrode 270 are removed. The portionsvia which the microcavity 305 is exposed are referred to as injectionopenings 307 a and 307 b. The two injection openings 307 a and 307 b maybe formed in one microcavity 305. For example, a first injection opening307 a exposing a side surface of a first edge of the microcavity 305,and a second injection opening 307 b exposing a side surface of a secondedge of the microcavity 305 may be formed. The first edge and the secondedge may face each other. For example, the first edge may be an upperedge of the microcavity 305, while the second edge may be a lower edgeof the microcavity 305.

Next, when an aligning agent containing an alignment material is drippedonto the substrate 110 using a spin coating method or an inkjet method,the aligning agent is injected into the microcavity 305 via theinjection holes 307 a and 307 b. When a curing process is performedafter the aligning agent is injected into the microcavity 305, asolution of the aligning agent is evaporated and the alignment materialremains at inner wall surfaces of the microcavity 305.

Accordingly, a first alignment layer 11 may be formed on the pixelelectrode 191, and a second alignment layer 21 may be formed under thecommon electrode 270. The first and second alignment layers 11 and 21are formed to face each other while interposing the microcavity 305therebetween. In some embodiments, the first and second alignment layers11 and 21 are connected to each other at a side wall of the edge of themicrocavity 305. In this case, the first and second alignment layers 11and 21 may be aligned in a direction perpendicular to the substrate 110,except at the side surface of the microcavity 305.

Next, when an inkjet method or a dispensing method is used to drip aliquid crystal (LC) material onto the substrate 110, the LC material isinjected through the injection openings 307 a and 307 b into themicrocavity 305 by a capillary force. Accordingly, an LC layer includingLC molecules 310 is formed inside the microcavity 305. The alignmentlayers 11 and 21 and the LC layer may not be formed in the dummymicrocavity 305 a.

Next, a material that does not react with the LC molecules 310 isdeposited on the third insulating layer 370 to form an encapsulationlayer 390. The encapsulation layer 390 is formed to cover the injectionopenings 307 a and 307 b and seal the microcavity 305, therebypreventing the LC molecules 310 formed inside the microcavity 305 frombeing leaked to the outside.

Next, the encapsulation layer 390 positioned on a boundary between thedisplay area DA and the peripheral area PA of the substrate 110 is cut.In addition, the encapsulation layer 390 positioned on a boundarybetween the peripheral area PA and an extra area EA of the substrate 110is cut. As such, after the encapsulation layer 390 and the substrate 110are respectively cut, the encapsulation layer 390 positioned in theperipheral area PA, and the extra area EA is separated from theperipheral area PA. That is, the encapsulation layer 390 positioned inthe peripheral area PA and the extra area EA of the substrate 110 isremoved along with the extra area EA of the substrate 110, and as shownin FIGS. 17 and 18, and only the display area DA and the peripheral areaPA of the substrate 110 remain. The encapsulation layer 390 remains onlyin the display area DA of the substrate 110.

In the cutting of the encapsulation layer 390, a laser may be irradiatedto the encapsulation layer 390 that is positioned on the boundarybetween the display area DA and the peripheral area PA of the substrate110. Due to the laser irradiation, a side surface of the encapsulationlayer 390 may include a heat-deformable portion. A region to which alaser is irradiated does not overlap the gate pad portion GP and thedata pad portion DP. Accordingly, damage to the gate contact assistant195 or the data contact assistant 197 may be prevented. In addition,since a photolithography process is not performed, contamination of theLC layer may be prevented.

However, the present disclosure is not limited thereto, and theencapsulation layer 390 may be mechanically cut. For example, a halfcutting method may be used to cut only the encapsulation layer 390 suchthat damage to the substrate 110 or the like positioned under theencapsulation layer 390 is prevented. In another example, a mechanicalcutting method may be used to cut the substrate 110.

It is illustrated that the dummy microcavity 305 a is positioned in alower part of a region where the encapsulation layer 390 is cut, but thepresent disclosure is not limited thereto. The dummy microcavity 305 amay not be positioned in the lower part of the region where theencapsulation layer 390 is cut, but may be covered only by theencapsulation layer 390.

During the removal of the encapsulation layer 390, the roof layer 360positioned in the peripheral area PA of the substrate 110 partiallyremains to form a pillar 500. During the removal of the encapsulationlayer 390, the roof layer 360 is divided into two parts, and one part isremoved along with the encapsulation layer 390 while the other partremains on the substrate 110. The second insulating layer 350 and thecommon electrode 270 positioned under the roof layer 360 may remaintogether.

The pillar 500 may include a first layer 510, a second layer 520positioned under the first layer 510, and a third layer 530 positionedunder the second layer 520. The first layer 510 may be made of the samematerial as and disposed on the same layer as the roof layer 360. Thefirst layer 510 may be formed to be thinner than the roof layer 360. Thesecond layer 520 may be made of the same material as and disposed on thesame layer as the second insulating layer 350. The third layer 530 maybe made of the same material as and disposed on the same layer as thecommon electrode 270. The pillar 500 may include only the third layer530, or may include only the third layer 530 and the second layer 520.

In the current exemplary embodiment, the dummy microcavity 305 a isformed in the peripheral area PA and is then removed such that the gatepad portion GP and the data pad portion DP are opened. Since theencapsulation layer 390 is formed to be extended to the peripheral areaPA and is then cut to be removed, the side surface of the encapsulationlayer 390 may have a steep slope, thereby reducing a bezel area. Inaddition, since the dummy microcavity 305 a is formed on the gate padportion GP and the data pad portion DP and is then removed, theencapsulation layer 390 or the like may be easily removed, and damage tothe gate pad portion GP and the data pad portion DP may be prevented.

Subsequently, although not illustrated, polarizing plates may be furtherattached to top and bottom surfaces of the display device. Thepolarizing plates may include a first polarizing plate and a secondpolarizing plate. The first polarizing plate may be attached to a bottomsurface of the substrate 110, and the second polarizing plate may beattached to the encapsulation layer 390.

Next, referring to FIGS. 19 to 21, a display device according to anexemplary embodiment will be described as follows. Since the displaydevice according to the current exemplary embodiment illustrated in FIG.19 to FIG. 21 has substantially the same configuration as the displaydevice according to the exemplary embodiment illustrated in FIGS. 1 to4, a description thereof may be omitted. The exemplary embodimentillustrated in FIGS. 19 to 20 differs from the aforementioned exemplaryembodiment in that a pillar does not include a layer that is made of thesame material as a common electrode, and will be described below indetail.

FIG. 19 is a partial top plan view of a display device, according to anexemplary embodiment. FIG. 20 is a cross-sectional view of the displaydevice, according to the exemplary embodiment taken along the line XX-XXof FIG. 19. FIG. 21 is a cross-sectional view of the display device,according to the exemplary embodiment taken along the line XXI-XXI ofFIG. 19.

Referring to FIGS. 19 to 21, the current exemplary embodiment is thesame as the aforementioned exemplary embodiment in that a thin filmtransistor Q including a gate electrode 124, a source electrode 173, adrain electrode 175, and a semiconductor 154 is formed on a display areaDA of a substrate 110. In addition, a gate pad 125 and a data pad 177are formed on a peripheral area PA of the substrate 110.

A common electrode 270 is formed on a first insulating layer 240. In theaforementioned exemplary embodiment, the common electrode 270 ispositioned on the microcavity 305, but in the current exemplaryembodiment, the common electrode 270 is positioned under a microcavity305.

The common electrodes 270 positioned inside a plurality of pixels PX maybe connected to each other via a connecting bridge 276 or the like, andmay transmit substantially the same voltage. The common electrode 270positioned inside each pixel PX may have a planar shape. The commonelectrode 270 may be made of a transparent metal oxide such as an indiumtin oxide (ITO) or an indium zinc oxide (IZO).

An interlayer insulating layer 250 is formed on the common electrode270. The interlayer insulating layer 250 may be made of an inorganicinsulating material such as a silicon nitride (SiNx) or a silicon oxide(SiOx).

A first contact hole 181 exposing at least a portion of the drainelectrode 175 is formed in the interlayer insulating layer 250, thefirst insulating layer 240, a light blocking member 220, and apassivation layer 180. In addition, a second contact hole 185 exposingat least a portion of the gate pad 125 is formed in the passivationlayer 180 and a gate insulating layer 140, and a third contact hole 187exposing at least a portion of the data pad 177 is formed in thepassivation layer 180.

A pixel electrode 191 is formed on the interlayer insulating layer 250.The pixel electrode 191 may include a plurality of branch electrodes1193 and a slit 93 positioned between the plurality of branch electrodes1193. The plurality of branch electrodes 1193 and the slit 93 of thepixel electrode 191 overlap the common electrode 270. The pixelelectrode 191 and the common electrode 270 are separated by theinterlayer insulating layer 250. The interlayer insulating layer 250serves to insulate the pixel electrode 191 from the common electrode270.

The pixel electrode 191 may include a protruding portion 1195 forconnection with a different layer. The protruding portion 1195 of thepixel electrode 191 is physically and electrically coupled to the drainelectrode 175 through the first contact hole 181 such that it is appliedwith a voltage from the drain electrode 175. The pixel electrode 191 maybe made of a transparent metal oxide such as an indium tin oxide (ITO)or an indium zinc oxide (IZO).

The pixel electrode 191 may include a curved side that is curved along acurved shape of the data line 171. For example, the pixel electrode 191may have a polygonal shape that includes a side that is bent at leastonce from a portion corresponding to a horizontal center line CL of thepixel PX.

In addition, a gate contact assistant 195 and a data contact assistant197 are positioned in the peripheral area PA of the substrate 110. Thegate contact assistant 195 and the data contact assistant 197 may bedisposed on the passivation layer 180.

The gate contact assistant 195 is connected to the gate pad 125 throughthe second contact hole 185. The gate contact assistant 195 may be madeof the same material as and disposed on the same layer as the pixelelectrode 191. The gate pad 125 and the gate contact assistant 195 arelaminated to form a gate pad portion GP.

The data contact assistant 197 is connected to the data pad 177 throughthe third contact hole 187. The data contact assistant 197 may be madeof the same material as and disposed on the same layer as the pixelelectrode 191. The data pad 177 and the data contact assistant 197 arelaminated to form a data pad portion DP.

The layout of the pixel and the shape of the thin film transistor thatare described above may be variously modified. In addition, the pixelelectrode 191 and the common electrode 270 may switch their positionswith respect to each other when they are sequentially laminated. In theabove description, it is described that the interlayer insulating layer250 is formed on the common electrode 270, and the pixel electrode 191is formed on the interlayer insulating layer 250. On the contrary, theinterlayer insulating layer may be formed on the pixel electrode, andthe common electrode may be formed on the interlayer insulating layer.Alternatively, the pixel electrode 191 may have a planar shape, and thecommon electrode 270 may include the branch electrodes and the slit.

A roof layer 360 is formed on the pixel electrode 191 to be spaced apartfrom the pixel electrode 191 by a predetermined distance. Themicrocavity 305 is formed between the pixel electrode 191 and the rooflayer 360. The microcavity 305 is surrounded by the pixel electrode 191and the roof layer 360.

Alignment layers 11 and 21 are formed above the pixel electrode 191 andunder the roof layer 360. The alignment layers may be horizontalalignment layers.

A liquid crystal (LC) layer containing LC molecules 310 is formed insidethe microcavity 305 that is positioned between the pixel electrode 191and the roof layer 360. The LC molecules 310 may have positivedielectric anisotropy or negative dielectric anisotropy. For example,the LC molecules 310 may be aligned such that their long axes aredisposed parallel to the substrate 110 when no electric field ispresent. That is, horizontal alignment may be achieved.

A pillar 500 is positioned in the peripheral area PA of the substrate110. The pillar 500 may be disposed on the passivation layer 180. Thepillar 500 may include a single layer or multiple layers. For example,the pillar 500 may include a first layer 510, and a second layer 520positioned under the first layer 510. The first layer 510 may be made ofthe same material as and disposed on the same layer as the roof layer360. The first layer 510 may be formed to be thinner than the roof layer360. The second layer 520 may be made of the same material as anddisposed on the same layer as the second insulating layer 350. Thepillar 500 may include only the second layer 520.

It is illustrated that the pillar 500 does not overlap the gate padportion GP and the data pad portion DP. However, the present disclosureis not limited thereto, and the pillar 500 may overlap a portion of thegate pad portion GP and the data pad portion DP.

A third insulating layer 370 is positioned on the roof layer 360, and anencapsulation layer 390 is formed on the third insulating layer 370. Theencapsulation layer 390 may encapsulate the microcavity 305.

The encapsulation layer 390 is positioned in the display area DA, and isnot positioned in the peripheral area PA. Accordingly, the gate padportion GP and the data pad portion DP may not be covered by theencapsulation layer 390, but may be exposed.

As in the aforementioned exemplary embodiment, a dummy microcavity maybe formed on the gate pad portion GP and the data pad portion DP, andthe encapsulation layer 390 and the substrate 110 may be respectivelycut to remove the encapsulation layer 390 positioned in the peripheralarea PA of the substrate 110, thereby allowing the gate pad portion GPand the data pad portion DP to be opened. In this case, damage to thegate pad portion GP and the data pad portion DP may be prevented.

While the present disclosure has been described in connection withexemplary embodiments, it is to be understood that the presentdisclosure is not limited to the disclosed embodiments, but, on thecontrary, is intended to cover various modifications and equivalentarrangements included within the spirit and scope of the presentdisclosure.

DESCRIPTION OF SYMBOLS

110: substrate 121: gate line 125: gate pad 171: data line 177: data pad191: pixel electrode 195: gate contact assistant 197: data contactassistant 270: common electrode 300: sacrificial layer 305: microcavity305a: dummy microcavity 310: LC molecule 360: roof layer 390:encapsulation layer 500: pillar 510: first layer 520: second layer 530:third layer GP: gate pad portion DP: data pad portion

What is claimed is:
 1. A manufacturing method of a display devicecomprising: forming a thin film transistor in a display area of asubstrate including a display area, a peripheral area, and an extraarea; forming a first electrode to be connected to the thin filmtransistor; forming a sacrificial layer on the first electrode; forminga roof layer on the sacrificial layer; forming a microcavity between thefirst electrode and the roof layer by removing the sacrificial layer;forming an encapsulation layer on the roof layer; cutting theencapsulation layer positioned on a boundary between the display areaand peripheral area of the substrate; cutting a boundary between theperipheral area and extra area of the substrate; and removing theencapsulation layer positioned in the peripheral area and extra area ofthe substrate, and the extra area of the substrate.
 2. The manufacturingmethod of claim 1, further comprising: forming a gate line on thesubstrate; and forming a data line on the substrate, wherein the gateline and the data line are connected to the thin film transistor.
 3. Themanufacturing method of claim 2, further comprising: forming, in theperipheral area of the substrate, a gate pad portion connected to thegate line; and forming, in the peripheral area of the substrate, a datapad portion connected to the data line.
 4. The manufacturing method ofclaim 3, further comprising: forming the sacrificial layer on the gatepad portion and the data pad portion; and forming a dummy microcavity.5. The manufacturing method of claim 4, further comprising: removing thedummy microcavity; and forming a pillar in the peripheral area of thesubstrate.
 6. The manufacturing method of claim 5, wherein the pillarincludes a first layer that is made of the same material as the rooflayer.
 7. The manufacturing method of claim 6, further comprising:forming a second electrode on the sacrificial layer; and forming aninsulating layer on the second electrode, wherein the pillar furtherincludes: a second layer that is positioned under the first layer and ismade of the same material as the insulating layer, and a third layerthat is positioned under the second layer and is made of the samematerial as the second electrode.
 8. The manufacturing method of claim6, further comprising: forming a second electrode; forming an interlayerinsulating layer interposed between the first electrode and the secondelectrode; and forming an insulating layer on the sacrificial layer,wherein the pillar further includes: a second layer that is positionedunder the first layer and is made of the same material as the insulatinglayer.
 9. The manufacturing method of claim 3, wherein the forming ofthe gate pad portion includes: forming a gate pad extended from an endportion of the gate line; and forming a gate contact assistant on thegate pad.
 10. The manufacturing method of claim 9, wherein the gate padis made of the same material as the gate line, and the gate contactassistant is made of the same material as the first electrode.
 11. Themanufacturing method of claim 3, wherein the forming of the data padportion includes: forming a data pad extended from an end portion of thedata line, and forming a data contact assistant on the data pad.
 12. Themanufacturing method of claim 11, wherein the data pad is made of thesame material as the data line, and the data contact assistant is madeof the same material as the first electrode.
 13. The manufacturingmethod of claim 1, further comprising: irradiating a laser to theencapsulation layer positioned on a boundary between the display areaand peripheral area of the substrate to cut the encapsulation layer. 14.The manufacturing method of claim 13, wherein a region to which a laseris irradiated does not overlap the gate pad portion or the data padportion.
 15. The manufacturing method of claim 13, wherein a sidesurface of the encapsulation layer includes a heat-deformable portion.